1. Field of the Invention
The present invention relates to clock circuits and, in particular, to an apparatus and method for obtaining stable delays for clock signals.
2. Background Art
Today""s highly integrated digital and mixed signal circuits require stable clock signals over various delay amounts. A conventional technique for delaying a clock signal is to stack invertors, i.e., coupling the output of each preceding invertor to the input of the subsequent invertor. The total clock delay is simply the sum of the nominal delay of each invertor. However, manufacturing process variations can cause the nominal delay of each inventor to be a different value. Moreover, voltage and temperature variations can also cause the amount of delay contributed by each invertor to vary. The cumulative error of these process, voltage and temperature (xe2x80x9cPVTxe2x80x9d) variations can cause hundreds of percent variations in the desired total delay achieved by stacking inventors.
High accuracy clock delay circuits typically comprise phase-locked loops (PLL), which consist of a phase detector, low pass filter and voltage-controlled oscillator, delay-locked loops (DLL), which consist of charge pumps and phase detectors, or the like. Voltage controlled delay lines utilize feedback circuits to track and adjust phase of the clock to achieve high delay accuracy as well. The drawbacks of such high accuracy circuits are the chip real estate, power and design resources needed for implementation. Months of circuit redesign are typically required when new, smaller line width manufacturing processes are developed.
What is needed is a circuit to obtain stable delays for clock signals without the complexity and cost of conventional high accuracy clock delay circuits.
The present invention is directed to an apparatus and method for generating a stable delay for a clock signal with respect to at least one of process, temperature and voltage variations.
In one embodiment of the present invention, a circuit comprises a current source to generate a constant current having a first value; first and second current over capacitance (I/C) stages coupled to the current source and between a supply voltage and ground; and a capacitor, having a second value and coupled to a node formed by an output of the first I/C stage and an input of the second I/C stage. Application of a clock signal to an input of the first I/C stage produces an output at a logic gate coupled to an output of the second I/C stage. The output has a stable delay based on the first and second values. Additionally, the first and second values (i.e., the value of the current or capacitance) can be changed to achieve a desired amount of the delay of the input clock signal.
The first and second I/C stages can each comprise a pair of complementary field effect transistors (FETs). The gates of the FETs of each respective I/C stage are coupled together to form the input of that stage, and drains of the FETs of each respective I/C stage are coupled together to form the output of that stage.
The current source can comprise a bandgap circuit. In one embodiment, an on-chip, switched capacitor is used to provide a constant resistance. The constant resistance, and a constant voltage provided by the bandgap circuit, produce the constant current.
In another embodiment, an off-chip, discrete resistor coupled to a constant voltage provided by the bandgap circuit are used to produce the constant current.
In yet another embodiment, the current source comprises cascoded current mirrors coupled between the supply voltage and the first and second I/C stages, and between the first and second I/C stages and ground.
These and other objects, advantages and features will become readily apparent in view of the following detailed description of the invention.